Nonvolatile semiconductor memory element excellent in charge retention properties and process for producing the same

ABSTRACT

A process for producing a nonvolatile semiconductor memory having a mixed or laminated structure of a hardly oxidizable material composed of a hardly oxidizable element having Gibbs&#39; free energy for forming oxide higher than that of Si under the same temperature condition at 1 atm and in temperature range of 0° C. to 1,200° C. and an oxide of an easily oxidizable material composed of an element having Gibbs&#39; free energy for forming oxide lower than that of Si under the same temperature condition at 1 atm in the temperature range and Si. The process includes forming a portion of the hardly oxidizable material and a portion of the oxide by physical forming method and carrying out heat treatment in oxidizing and reducing gas mixture. The ratio of the gases and the temperature are controlled so that the hardly oxidizable material is reduced and the oxide is oxidized in the temperature range.

TECHNICAL FIELD

The present invention relates to a nonvolatile semiconductor memoryelement excellent in charge retention properties, which has aconstruction constituted by a plurality of materials containing elementshaving different Gibbs' formation free energies for forming oxides, thatare different from one another by a difference in a level of thedifference between those of Si and a transition metal such as Ni, W orCo; and to a process for producing such a device. The present inventionparticularly relates to a nonvolatile semiconductor memory elementexcellent in charge retention properties, which has the aboveconstruction constituted by a hardly oxidizable material and an oxide ofeasily oxidizable material, which is produced by decreasing defects inthe oxide due to oxygen-shortage such as oxygen-shortage type defects orfree valencies, by oxidation, and reducing the hardly oxidizablematerial. Hereinafter Gibbs' formation free energy for forming an oxideis also simply referred to as oxide formation free energy.

BACKGROUND ART

Heretofore, for portable information terminal devices such as cellphones, flash memories are widely used as memory devices capable ofmemorizing in a nonvolatile manner. The reason is that high densityintegration of flash memory is relatively easy, production technique forflash memory is highly compatible with those of conventional logic orDRAM devices, and cost of flash memory is relatively low. However, it isnot easy to form a thin film of insulator surrounding a floating gate ofa flash memory.

In order to secure charge retention of floating gate, that is,reliability of memory retention of flash memory, it is necessary to makethe film thickness of the insulator surrounding a floating gate at leasta predetermined thickness. Thus, since forming of thin film of insulatoris difficult, in a flash memory of conventional structure, progresstoward high performance of device such as miniaturization, high speed,low voltage operation and low power consumption, becomes difficult, andthere is a prediction that progress toward high performance reaches alimit as early as year 2007.

As a technique solving the above problem of securing reliability ofcharge retention and achieving a thin film of insulator at the same timein a single floating gate type flash memory, a technique of dividing thefloating gate into a plurality of pieces, has been proposed. As anexample of specific method for dividing a floating gate into a pluralityof pieces, there is a method of forming a large number of Si ultrafineparticles for each memory element and using a group of such Si ultrafineparticles as a floating gate (for example, Patent Document 1). By thusdividing a floating gate, even when leakage of retained charge occurs,loss of accumulated electric charge can be limited to a small region,whereby requirement for reliability of insulator can be eased. A flashmemory having such a floating gate divided into a plurality of pieces isreferred to as a divided floating gate type flash memory, and theabove-mentioned flash memory of conventional structure is referred to asa is single floating gate type flash memory in this document.

The technique of dividing a floating gate contributes to improvement ofreliability of charge retention of an insulator, and enables forming ofa thin film of insulator, and for this reason, the technique is one oftechniques for solving the above-mentioned problem of conventionalsingle floating gate type flash memory.

Further, a technique is studied, in which the ultrafine particlesserving as a floating gate is not made of Si but made of a metal. It isknown that a floating gate constituted by metal ultrafine particles canimprove charge retention performance more than Si ultrafine particlefloating gate (for example, Patent document 2). The reason is becausemetal has a work function relatively larger than the electron affirmityof Si, and accordingly, a potential barrier for electric charge retainedin the metal ultrafine particle floating gate is higher than that forelectric charge in the Si ultrafine particle floating gate.

Here, in the technique for forming a metal ultrafine particle floatinggate disclosed in Patent Document 2, an insulation film (hereinafterreferred to as gate insulation film) deposited between the metalultrafine particle floating gate and a control gate, is formed by a CVDmethod, there is a case where the metal ultrafine particles are oxidizedat a time of forming the gate insulation film. It is pointed out thatwhen the metal ultrafine particles are thus oxidized, the number ofmetal ultrafine particles effectively working for charge retention maydecrease.

As a technique for preventing such an oxidation of metal ultrafineparticles, a technique of forming a gate insulation film by using asputtering method is disclosed (for example, Patent Document 3). Since asputtering method enables to form a film at a lower temperature ascompared with a CVD method or a thermal oxidation method in general, andaccordingly, it becomes possible to deposit a gate insulation film onthe metal ultrafine particles while oxidation of the metal ultrafineparticles is suppressed.

Patent Document 1: JP-A-11-186421

Patent Document 2: JP-A-2003-51498

Patent Document 3: JP-A-2003-86715

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention

However in such a conventional producing technique of nonvolatilesemiconductor memory element employing a sputtering method, an insulatorsuch as SiO₂ formed by a sputtering method, usually has high density ofoxygen-shortage type defects and has a composition ratio of excess Si inmany cases. Further, since many free valencies (dangling bonds) arecontained, there is a problem that such an insulator has low insulationperformance as compared with SiO₂ layer formed by using a CVD method ora thermal oxidation method.

Accordingly, employment of a CVD method or a thermal oxidation methodand employment of a sputtering method cause a problem of oxidation ofmetal ultrafine particles and a problem of low insulation performance ofan insulator, respectively. As a result, there occurs such a problemthat high charge retention performance of the metal ultrafine particlefloating gate can not be sufficiently exhibited or that thin film ofinsulator can not be sufficiently achieved, and element performance ofnonvolatile semiconductor memory element having a metal fine particlefloating gate has not been sufficiently exhibited.

The present invention has been made to solve these problems, and thepresent invention provides a nonvolatile semiconductor memory elementcapable of improving insulation performance of an insulator surroundinga floating gate composed of e.g. metal fine particles, and capable ofdecreasing the ratio of oxidized metal portion in the floating gate, andthe present invention provides a process for producing such an element.

Means of Solving the Problem

Considering the above points, a first aspect of the present inventionprovides a process for producing a nonvolatile semiconductor memoryelement having a mixed or laminated structure of:

a hardly oxidizable material composed of a hardly oxidizable elementhaving a Gibbs' formation free energy for forming oxide higher than theGibbs' formation free energy of Si for forming oxide under the sametemperature condition at 1 atm and in a temperature range of from 0° C.to 1,200° C.: and

an oxide of an easily oxidizable material composed of an element havinga Gibbs' formation free energy for forming oxide lower than the Gibbs'formation free energy of Si for forming oxide under the same temperaturecondition at 1 atm in the temperature range of from 0° C. to 1,200° C.,and Si;

the process comprising;

a step of forming a portion made of a hardly oxidizable material and aportion made of the oxide of the easily oxidizable material by aphysical forming method; and

a step of carrying out a heat treatment in a mixed gas of an oxidizinggas functioning as an oxidizing agent and a reducing gas functioning asa reducing agent, wherein the mixture ratio of the oxidizing gas and thereducing gas and the temperature are controlled so that the hardlyoxidizable material is reduced and the oxide of the easily oxidizablematerial is oxidized in a temperature range of from 0° C. to 1,200° C.

By this construction, in a nonvolatile semiconductor memory elementhaving a construction that a hardly oxidizable material composed of e.g.W, Ni or Co is used as an ultrafine particle floating gate or a singlefloating gate and that an oxide of easily oxidizable material such asSiO₂ is used as an insulator surrounding the floating gate, wherein theultrafine particle floating gate or the single floating gate and theinsulator are formed by using a physical forming method, it is possibleto bond oxygen atoms to oxygen-shortage type defects or free valenciesetc. in an insulator such as SiO₂ while the ultrafine particle floatinggate or the single floating gate is not oxidized or while it is reduced,whereby it is possible to improve insulating performance of theinsulator surrounding the floating gate such as the metal ultrafineparticle floating gate and to decrease the ratio of oxidized metalultrafine particles in the floating gate as compared with conventionalelements, whereby it is possible to realize a process for producingnonvolatile semiconductor memory element having high charge retentionperformance. Here, “hardly oxidizable” in the present invention means aproperty that a material is more hardly oxidizable than Si, andspecifically, a property that a Gibbs' formation free energy for formingoxide of the material is higher than an oxide-formation free energy ofSi in an environment of 1 atm and the same temperature, is defined as aproperty of more hardly oxidizable than Si. Further, an element havingsuch a property is defined as a hardly oxidizable element, and amaterial composed of a hardly oxidizable element is defined as a hardlyoxidizable material. On the other hand, “easily oxidizable” in thepresent invention means a property that a material is more easilyoxidizable than Si, and specifically, a property that Gibbs' formationfree energy for forming oxide of the material is equal or lower than anoxide-formation free energy of Si in an environment of 1 atm and thesame temperature, is defined as a property of more easily oxidizablethan Si. Further, in the same manner as the case of the above hardlyoxidizable property, easily oxidizable element and easily oxidizablematerial are defined correspondingly.

Further, a second aspect of the present invention provides a process forproducing a nonvolatile semiconductor memory element having a mixed orlaminated structure of:

a hardly oxidizable material composed of a hardly oxidizable elementhaving a Gibbs' formation free energy for forming oxide higher than theGibbs' formation free energy of Si for forming oxide under the sametemperature condition at 1 atm and in a temperature range of from 0° C.to 1,200° C.; and

an oxide of an easily oxidizable material composed of an element havinga Gibbs' formation free energy for forming oxide lower than the Gibbs'formation free energy of Si for forming oxide under the same temperaturecondition at 1 atm in the temperature range of from 0° C. to 1,200° C.,and Si;

the process comprising;

a step of forming a portion made of the hardly oxidizable material by aphysical forming method and forming a portion made of the oxide of theeasily oxidizable material by a chemical forming method; and

a step of carrying out a heat treatment in a mixed gas of an oxidizinggas functioning as an oxidizing agent and a reducing gas functioning asa reducing agent, wherein the mixture ratio of the oxidizing gas and thereducing gas and the temperature are controlled so that the hardlyoxidizable material is reduced and the oxide of the easily oxidizablematerial is oxidized in a temperature range of from 0° C. to 1,200° C.

By this construction, in a nonvolatile semiconductor memory elementhaving a construction that a hardly oxidizable material composed of e.g.W, Ni or Co is used as an ultrafine particle floating gate or a singlefloating gate and using an oxide of easily oxidizable material such asSiO₂ is used as an insulator surrounding the floating gate, wherein theultrafine particle floating gate or the single floating gate is formedby using a physical forming method and the insulator is formed by usinga chemical forming method, it is possible to bond oxygen atoms tooxygen-shortage type defects or free valencies in an insulator such asSiO₂ by reducing the ultrafine particle floating gate or the singlefloating gate without oxidizing them, whereby it is possible to improveinsulating performance of the insulator surrounding a floating gate suchas the metal ultrafine particle floating gate and to decrease the ratioof oxidized metal ultrafine particles in the floating gate as comparedwith conventional elements, whereby it is possible to realize a processfor producing nonvolatile semiconductor memory element having highcharge retention performance.

Further, a third aspect of the present invention provides a process forproducing a nonvolatile semiconductor memory element having a mixed orlaminated structure of:

a hardly oxidizable material composed of a hardly oxidizable elementhaving a Gibbs' formation free energy for forming oxide higher than theGibbs' formation free energy of Si for forming oxide under the sametemperature condition at 1 atm and in a temperature range of from 0° C.to 1,200° C.: and

an oxide of an easily oxidizable material composed of an element havinga Gibbs' formation free energy for forming oxide lower than the Gibbs'formation free energy of Si for forming oxide under the same temperaturecondition at 1 atm in the temperature range of from 0° C. to 1,200° C.,and Si;

the process comprising:

a step of forming a portion made of a hardly oxidizable material byforming a tentative forming layer in which the hardly oxidizablematerial and a first oxide of the easily oxidizable material are mixedor laminated, by a physical forming method, followed by selectivelyremoving the first oxide of the easily oxidizable material in thetentative forming layer;

a step of forming a portion made of the oxide of the easily oxidizablematerial by depositing a second oxide of the easily oxidizable materialthat is the same or different from the first oxide of the easilyoxidizable material, by using a physical forming method or a chemicalforming method after the first oxide of the easily oxidizable materialin the tentative forming layer is selectively removed; and

a step of carrying out a heat treatment in a mixed gas of an oxidizinggas functioning as an oxidizing agent and a reducing gas functioning asa reducing agent, wherein the mixture ratio of the oxidizing gas and thereducing gas and the temperature are controlled so that the hardlyoxidizable material is reduced and the second oxide of the easilyoxidizable material is oxidized in a temperature range of from 0° C. to1,200° C.

By this construction, in a nonvolatile semiconductor memory elementhaving a construction that a hardly oxidizable material composed of e.g.W, Ni or Co is used as an ultrafine particle floating gate or a singlefloating gate and an oxide of an easily oxidizable material such as SiO₂is used as an insulator surrounding the floating gate, wherein theultrafine particle floating gate or the single floating gate is formedby using a physical forming method and the insulator is formed by usinga physical forming method or a chemical forming method, it is possibleto bond oxygen atoms to oxygen-shortage type defects or free valenciesin an insulator such as SiO₂ while the ultrafine particle floating gateor the single floating gate is not oxidized or while it is reduced,whereby it is possible to improve insulating performance of theinsulator surrounding the floating gate such as the metal ultrafineparticle floating gate and to decrease the ratio of oxidized metalultrafine particles in the floating gate, whereby it is possible torealize a process for producing nonvolatile semiconductor memory elementhaving high charge retention performance. Further, since the first oxidesuch as SiO₂ of the easily oxidizable material containing relativelylarge amount of oxygen-shortage type defects in the tentative forminglayer formed by using a physical forming method, is selectively removed,and the second oxide of the easily oxidizable material having littleoxygen-shortage type defects, is subsequently deposited, it is possibleto realize a process for producing nonvolatile semiconductor memoryelement having an insulator containing further little oxygen-shortagetype defects.

Further, a fourth aspect of the present invention provides the processfor producing a nonvolatile semiconductor memory element, wherein changeamount of Gibbs' free energy of the oxidizing gas required for oxidationreaction with the easily oxidizable material is negative in thetemperature range of from 0° C. to 1,200° C., change amount of Gibbs'free energy of the reducing gas required for reduction reaction with theoxide of the hardly oxidizable material is negative in the temperaturerange of from 0° C. to 1,200° C., and change amount of Gibbs' freeenergy of the reducing gas required for reduction reaction with theoxide of the easily oxidizable material is positive in the temperaturerange.

By this construction, besides the effect of any one of the first tothird aspects, in a range of from 0° C. to 1,200° C., the oxidizing gascan appropriately oxidizes an easily oxidizable material such as Siwithout oxidizing, the ultrafine particle floating gate or the singlefloating gate, and the reducing gas can appropriately reduce theultrafine particle floating gate or the single floating gate withoutreducing the oxide such as SiO₂ of an easily oxidizable material.Accordingly, it is possible to regulate the oxidation power of theoxidizing gas used and reduction power of the reducing gas used, it ispossible to properly perform the heat treatment for oxidation andreduction, and to realize a process for producing nonvolatilesemiconductor memory element having high charge retention performance.

Further, a fifth aspect of the present invention provides the processfor producing a nonvolatile semiconductor memory element according toany one of the first to fourth aspects, wherein the oxidizing gascontains H₂O and the reducing gas contains H₂.

By this construction, besides the effect of any one of the above firstto fourth aspects, since hydrogen and water vapor are widely used in thefield of semiconductor element manufacturing and easy to handle, areused in the mixed gas, it is possible to realize a process capable ofproducing easily, safely and with good reproducibility a nonvolatilesemiconductor memory element having high charge retention performance.

Further, a sixth aspect of the present invention provides the processfor producing a nonvolatile semiconductor memory element excellent incharge retention characteristics according to any one of the first tofifth aspects, wherein the heat treatment is carried out in a mixed gasof the oxidizing gas and the reducing gas so that the hardly oxidizablematerial is reduced and the oxide of the easily oxidizable material isoxidized, and subsequently, a further heat treatment is carried out in apredetermined inert gas atmosphere or is under a reduced pressure.

By this construction, besides the effect of any one of the above firstto fifth aspects, since a further heat treatment is carried out in apredetermined inert gas atmosphere or under a reduced pressure after theoxidation reduction treatment is performed, it is possible to realize aprocess for producing nonvolatile semiconductor memory element capableof effectively removing by-product material such as OH groups which mayremain after the oxidation reduction treatment. Here, OH groups that mayremain after the oxidation reduction treatment, may cause adverseaffects such that it decreases melting point of the oxide or decreasesinsulation performance of the oxide.

Further, a seventh aspect of the present invention provides anonvolatile semiconductor memory element having the hardly oxidizablematerial, and produced by using the process for producing nonvolatilesemiconductor memory element as defined in any one of the above first tosixth aspects.

By this construction, it is possible to realize a nonvolatilesemiconductor memory element providing an effect of any one of the abovefirst to sixth aspects.

EFFECTS OF THE INVENTION

According to the present invention, in a nonvolatile semiconductormemory element having a construction that a hardly oxidizable materialcomposed of e.g. W, Ni or Co is used as an ultrafine particle floatinggate or a single floating gate and an oxide such as SiO₂ of an easilyoxidizable material is used as an insulator encompassing the floatinggate, wherein the ultrafine particle floating gate or a single floatinggate is formed by using a physical forming method and the insulator isformed by using a physical forming method or a chemical forming method,it is possible to bond oxygen atoms with oxygen-shortage type defects orfree valencies in an insulator such as SiO₂ while the ultrafine particlefloating gate or the single floating gate is not oxidized or while it isreduced, whereby it is possible to improve insulation performance of theinsulator surrounding the floating gate such as the metal ultrafineparticle floating gate, and to decrease the ratio of oxidized metalultrafine particles in the floating gate, whereby it is possible toprovide a nonvolatile semiconductor memory element having high chargeretention performance and a process for producing such a nonvolatilesemiconductor memory element.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1: An explanation view schematically shoring an example of a crosssectional structure of nonvolatile semiconductor memory elementaccording to an embodiment of the present invention.

FIG. 2: A view explaining an oxidation-reduction conditions in aconstruction that ultrafine particles are made of W or Ni and matrixinsulator is made of SiO₂.

FIG. 3: A flow chart for explaining a production process of nonvolatilesemiconductor memory element according to Example 1 of the presentinvention.

FIG. 4: An explanation view explaining S101 step according to Example 1of the present invention.

FIG. 5: An explanation view explaining S102 step according to Example 1of the present invention.

FIG. 6: An explanation view explaining S103 step according to Example 1of the present invention.

FIG. 7: An explanation view explaining S104 step according to Example 1of the present invention.

FIG. 8: An explanation view explaining S105 step according to Example 1of the present invention.

FIG. 9: An explanation view explaining S106 step according to Example 1of the present invention.

FIG. 10: An explanation view explaining S107 step according to Example 1of the present invention.

FIG. 11: An explanation view explaining S108 step according to Example 1of the present invention.

FIG. 12: An explanation view explaining S109 step according to Example 1of the present invention.

FIG. 13: An explanation view explaining S110 step according to Example 1of the present invention.

FIG. 14: An explanation view explaining S111 step according to Example 1of the present invention.

FIG. 15: An explanation view explaining S112 step according to Example 1of the present invention.

FIG. 16: An explanation view explaining S114 step according to Example 1of the present invention.

FIG. 17: An explanation view schematically showing an example of crosssectional structure of a nonvolatile semiconductor memory elementaccording to Example 2 of the present invention.

FIG. 18: An explanation view explaining S103 step according to Example 2of the present invention.

FIG. 19: An explanation view explaining S104 step according to Example 2of the present invention.

FIG. 20: An explanation view explaining S105 step according to Example 2of the present invention.

FIG. 21: A view explaining oxidation reduction conditions in aconstruction that ultrafine particles are made of CoO and matrixinsulator is made of SiO₂.

FIG. 22: An explanation view explaining S106 step and S107 stepaccording to Example 2 of the present invention.

FIG. 23: A view schematically showing a cross sectional structure of anelement after S115 step according to Example 2.

FIG. 24: An explanation view schematically showing an example of crosssectional structure of a nonvolatile semiconductor memory elementaccording to Example 3 of the present invention.

FIG. 25: An explanation view explaining S104 step according to Example 3of the present invention.

FIG. 26: An explanation view illustrating selective removal of SiO₂matrix insulator according to Example 3 of the present invention.

FIG. 27: An explanation view illustrating S105 step according to Example3 of the present invention.

FIG. 28: A view illustrating oxidation reduction conditions in aconstruction that ultrafine particles are made of W, tunnel insulationfilm is made of high dielectric constant material of HfO₂ silicate typeand gate insulation film is made of SiO₂.

FIG. 29: A view schematically showing a cross sectional structure of theelement after S115 step according to Example 3 of the present invention.

EXPLANATION OF NUMERALS

-   -   1: Semiconductor substrate,    -   2: element isolation,    -   3, 23, 33: tunnel insulation film,    -   4, 24, 34: charge retention layer,    -   4 a 1, 24 a 1, 34 a 1: ultrafine particles,    -   4 b: matrix insulator,    -   4 c, 5 b, 34 c: oxygen shortage type defect,    -   4 d, 5 c, 34 d: free valency    -   4 e, 5 d: OH group,    -   5, 5 a, 25, 35: gate insulation film,    -   6: control gate,    -   7: source region,    -   7 a, 8 a: shallow junction region,    -   7 b, 8 b: contact region,    -   8: drain region,    -   9: sidewall,    -   10: halo ion implantation region,    -   21: screen oxide film,    -   24 f: oxidized portion,    -   34 b: SiO₂ matrix insulator,    -   100, 200, 300: nonvolatile semiconductor memory element

BEST MODE FOR CARRYING OUT THE INVENTION

From now, embodiments of the present invention will be described withreference to drawings.

Embodiment

FIG. 1 is an explanation view schematically showing an example of crosssectional structure of a nonvolatile semiconductor memory elementaccording to an embodiment of the present invention. In FIG. 1, anonvolatile semiconductor memory element 100 is formed on asemiconductor substrate 1, and is isolated by element isolation 2. Here,the semiconductor substrate 1 in FIG. 1 is a semiconductor substrate ofp-type, and the element isolation 2 is one formed by using a STI(Shallow Trench Isolation) technique.

The nonvolatile semiconductor memory element 100 has a structure that onthe semiconductor substrate 1, a tunnel insulation film 3, a chargeretention layer 4 for retaining an electric charge, a gate insulationfilm 5 and a control gate 6 laminated in this order. The chargeretention layer 4 has a structure that ultrafine particles 4 a 1functioning as a floating gate is dispersed in a matrix insulator 4 bwith high density.

Here, the control gate 6 forms a channel on a surface of thesemiconductor substrate 1 according to an applied voltage and injects orreleases an electric charge to/from the charge retention layer 4. On thesurface of the semiconductor substrate 1, a source region 7 and a drainregion 8 are formed. The source region 7 and the drain region 8 areregions doped with n-type impurities, and have contact regions 7 b, 8 bfor obtaining an ohmic contact with an Al circuit, and shallow junctionregions 7 a, 8 a containing relatively low concentration of n-typeimpurities for serving to realize high withstand voltage of diffusionlayer and to suppresses excess generation of hot carriers.

The above source region 7 and drain region 8 are each formed so that itsregion (gate overlap region) overlapped with a region where the chargeretention layer 4 and the control gate 6 are formed, is minimized byusing a technique of so-called self alignment. This construction is forthe purpose of reducing parasitic capacitance formed by the overlap.Further, in a case of element having a gate length of about 0.3 μm orsmaller, it is preferred to form halo ion implantation regions 10 in thesemiconductor substrate 1 in regions more inside from the shallowjunction regions 7 a, 8 a, by ion-implanting p-type impurities havingthe same polarity as that of the semiconductor substrate 1 so that theconcentration of p-type impurities is increased. This halo ionimplantation exhibits an effect of decreasing leakage between the sourceand the drain occurred at a portion slightly deeper than the vicinity ofsemiconductor surface where a channel is formed when the gate length isshort.

As the semiconductor substrate 1, a single crystal substrate of Si orGe, a single crystal substrate of SiGe, a single crystal substrate ofSiC, or a SOI (silicon on insulator) substrate having a structure that alayer of any of these single crystals is formed on an insulator, may beemployed. A single crystal substrate of Si is preferred for the reasonthat its physical properties are identified, and it is easily available.As a material of semiconductor substrate (or layer) for contributinghigh speed operation of element, a single crystal of e.g. Ge or SiGe ora single crystal of Si having a strain from the viewpoint that theyimprove carrier mobility. Further, from the viewpoint of decreasingdelay time by decreasing parasitic capacitance of substrate depletionlayer, or for improving subthreshold properties, a SOI substrate ispreferred. Further, for operation under high temperature environment ora high voltage drive, e.g. a single crystal substrate of SiC ispreferred.

Here, for the reason that electrons having higher mobility than holescan be used as carriers, the above semiconductor substrate is preferablya p-type semiconductor.

From now, explanation will be made under assumption that thesemiconductor substrate 1 is a single crystal substrate of Si. In theabove, the element isolation is a STI type element isolation, but whenhigh integration density is not required, a so-called LOCOS (localoxidation of silicon) type element isolation may also employed.

The tunnel insulation film 3 may be formed by using an oxide film suchas a SiO₂ film, a nitride film or any of other insulative materials, andamong these, a SiO₂ film is preferred for achieving good elementoperation since dense and stable SiO₂ film can be obtained by subjectingSi to thermal oxidation. Further, as a tunnel insulation film 3, a highdielectric film made of a high dielectric material (high-k material)such as SiO_(x)N_(y) or a Hf type oxide, is preferred for the followingreasons.

Namely, by employing a dielectric film made of a is high dielectricmaterial, it is possible to increase capacitive coupling propertybetween the semiconductor substrate 1 and the control gate 6 to suppressshort-channel effect, and it is possible to suppress diffusion of metalelements from a floating gate to the semiconductor substrate 1 when themetal is employed for the floating gate in the charge retention layer 4on the tunnel insulation film 3. Here, the above x and y satisfies 0≦x<2and 0<y≦4/3. Here, it is preferred that the x and y further satisfy acondition 2x+3y=4 at the same time for reducing free valencies.

The charge retention layer 4 is formed on the tunnel insulation film 3and has ultrafine particles 4 a 1 for retaining an electric charge and amatrix insulator 4 b in which the ultrafine particles 4 a 1 aredispersed. Various methods for forming the charge retention layer 4 havebeen developed, and as described in e.g. JP-A-2004-55969, a method(hereinafter referred to as simultaneous sputtering method) ofsimultaneously sputtering using both a target for ultrafine particles 4a 1 made of a material having a large work function and a target for thematrix insulator 4 b, is preferred for the following reasons.

By using the above forming method of charge retention layer, a filmhaving a structure that metal ultrafine particles 4 a 1 is highlydensely dispersed in the matrix insulator 4 b, is obtained. By employinga charge retention layer 4 in which ultrafine particles 4 a 1 of a metalhaving a large work function are highly densely dispersed, the followingmerits are obtained. Namely, since the material of ultrafine particlesforming a floating gate is a metal having a large work function, it ispossible to retain electric charge at a deeper energy level as comparedwith a semiconductor, which increases a potential barrier at aninterface with an insulator. As a result, it is possible to increase apotential barrier of the tunnel insulation film 3, it is possible tosuppress loss of electric charge from the ultrafine particles bytunnel-leakage, and it is possible to increase charge retentionperformance.

Further, since a large number of metal ultrafine particles forming afloating gate are present in a memory element with high density and theparticles are insulated one another by a matrix insulator, even whene.g. insulation breakage occurs in the tunnel insulation film, theamount of lost electric charge can be limited to a narrow area andminimum amount. Thus, division of floating gate provides an effect oftolerating occurrence of insulation breakage to a certain extent, whichcontributes to improve yield of the element.

The more number of floating gates are contained in an element, thehigher the above effect can be increased, and this can be achieved byforming ultrafine particles at a high density. The size of eachultrafine particle is preferably as small as possible. Here, since it ispossible to disperse a large number of extremely small metal ultrafineparticles of a diameter of about 1 to 3 nm, densely in a matrixinsulator by employing the above simultaneous sputtering method, themethod for forming ultrafine particles is extremely suitable from theviewpoint of the above charge retention performance and insulationbreakage, etc.

The reason why it is possible to disperse the ultrafine particles in asmall size at high density by using the above simultaneous sputteringmethod, is that since the metal ultrafine particles and the matrixinsulator are formed simultaneously, the matrix insulator covers aroundeach of the metal ultrafine particles when the ultrafine particles areformed, and the matrix insulator functions to suppress particle growthof the metal ultrafine particles. Further, under the growth conditionsin which migration is sufficiently allowed, metal fine particles on asubstrate generally grow to a predetermined size determined bythermodynamics. However, in a sputtering method, since metal fineparticles are formed at a relatively low temperature, it becomespossible to stop the reaction for particle growth in a non-equilibriumstate before the particles grows to the thermodynamically determinedsize. For these reasons, as the method for forming charge retentionlayer, the simultaneous sputtering method using a metal target and aninsulator target, is extremely preferred.

Further, a metal for forming the metal ultrafine particles preferablyhas a work function of not only large but also close to the workfunctions of the semiconductor substrate and the control gate, for thepurpose of increasing charge retention performance. Here, the workfunction of semiconductor substrate means an energy difference betweenits Fermi level and vacuum level. Specifically, it is preferred that themetal has a work function of at least 4.2 eV and the difference from thework function of semiconductor substrate or control gate is at most 0.5eV.

Further, the metal to be used for forming the metal ultrafine particlespreferably has a high melting point and made of an element whoseionizing energy in a semiconductor is sufficiently smaller than a halfof energy band (hereinafter referred to as gap energy) in a band gap ofthe semiconductor, for the reasons that a high melting point metal isstable in a high temperature environment in the semiconductormanufacturing process and that when the metal is diffused through thetunnel insulation film to reach the semiconductor substrate, the metaldoes not affect generation and recoupling of electron and hole in thechannel.

Specifically, the metal preferably has a melting point of at least1,400° C. and its ionizing energy is preferably at least 0.1 eV smallerthan a half of the gap energy. By putting together the viewpoints ofwork function, melting point and ionizing energy, the metal for formingmetal ultrafine particles is specifically preferably W, Mo, Ti, Pd, Ni,Ta, Cr or the like, but it may be Os, R_(e), Nb, Ru, Rh or Pt as well.

Further, in order to obtain insulation between adjacent metal ultrafineparticles, the distance between metal ultrafine particles is preferablylarger than the predetermined distance, and it is specificallypreferably at least 1 nm. Further, when the distance is too large, highdensity of the ultrafine particles is hard to obtain, and accordingly,the distance is preferably at most 5 nm. The distance between adjacentmetal ultrafine particles substantially depends on the mixture ratio ofthe metal and the insulator in a target used for sputtering, and thedistance between adjacent metal ultrafine particles can be controlled byadjusting the mixture ratio. Here, the distance between ultrafineparticles in this explanation means the shortest distance from aninterface between an ultrafine particle and the matrix insulator to aninterface between another ultrafine particle and the matrix insulatorwhen these two ultrafine particles are adjacent to each other.

Meanwhile, the matrix insulator 4 b is preferably a material having lowelectron affirmity which easily becomes amorphous, for the purpose ofincreasing charge retention performance. Further, the matrix insulator 4b preferably has a high melting point for the reason that such a matrixinsulator 4 b is stable in a high temperature environment in thesemiconductor manufacturing process. Specifically, the electronaffirmity is preferably at most 1.0 eV, and the melting point ispreferably at least 1,400° C. By putting together the viewpoints ofelectron affirmity, easiness of forming amorphous and the melting point,the matrix insulator 4 b is preferably an amorphous material made ofe.g. SiO₂. As an alternative, an amorphous Al₂O₃ or TiO₂ may also beemployed.

However, when e.g. an oxide is employed as the matrix insulator 4 b ofthe charge retention layer 4, an oxide usually contains a large numberof defects due to shortage of oxygen such as oxygen shortage typedefects or free valencies (hereinafter simply referred to as defects dueto oxygen shortage; the corresponding definition is applied also todefects such as shortage type defects or free valencies in an insulatorsuch as a nitride other than oxide), there is the following problem.Namely, an electric charge retained in an ultrafine particle easilymoves to adjacent another ultrafine particle via such a defect due tooxygen shortage, to cause deterioration of insulation between ultrafineparticles.

In order to avoid such deterioration of insulation, it is necessary tobond oxygen atoms to a large number of defects due to oxygen shortagesuch as oxygen shortage type defects or free valencies contained in thematrix insulator of the charge retention layer, to remove these defectsdue to oxygen shortage. Here, removal of these defects due to oxygenshortage needs to be carried out so as not to oxidize ultrafineparticles. A specific method to suppress oxidization of ultrafineparticles and at the same time to bond oxygen atoms to defects of theoxide, will be described later.

The method for forming the gate insulation film 5 formed on the chargeretention layer 4 are roughly categorized into physical forming methodsand chemical forming methods, and any one of these methods may be usedfor forming the gate insulation film 5, but these methods each has amerit and demerit. First of all, in a physical forming method such as asputtering method, since the film-forming temperature is relatively low,there is a merit that oxidation of a floating gate 4 a 1 in theunderlying charge retention layer 4 can be suppressed. However, since agate insulation film formed by this method contains many defects due tooxygen shortage, its insulation performance is generally low.

Accordingly, in a case of forming the gate insulation film 5 by aphysical forming method, an effect of suppressing ultrafine particles 4a 1 present in the underlying charge retention layer 4, is high, butinsulation performance of the gate insulation film 5 itself becomes low.As a result, the possibility that an electric charge accumulated in theultrafine particles 4 a 1 leak through a large number of defectivelevels present in the gate insulation film 5 into the control gate 6,increases, and the charge retention performance of the elementdecreases.

On the other hand, in a chemical forming method that is more widely usedfor forming an insulator than a physical forming method, the density ofdefects due to oxygen shortage in an insulator formed, is low, and itsinsulation performance is generally higher than that obtained by aphysical forming method. However, in a chemical forming method, thefilm-forming temperature is generally high, and there is a demerit thatthe ultrafine particles 4 a 1 in the underlying charge retention layer 4tend to be oxidized at a time of film-forming. Accordingly, in a case offorming the gate insulation film 5 by a chemical forming method, theinsulation performance of the gate insulation film 5 itself is high, butthe ultrafine particles 4 a 1 contained in the underlying chargeretention layer 4 tend to be oxidized. Namely, a situation opposite tothat in a case of using a physical forming method, is realized. When thefloating gate 4 a 1 is oxidized, an energy level for retaining electriccharge increases, and as a result, a potential barrier decreases and thecharge retention performance decreases.

As described above, two types of methods considerable as methods forforming the gate insulation film 5, namely, a physical forming methodand a chemical forming method, each has a problem not desirable from theviewpoint of charge retention performance of an element. Problems to besolved in these two forming methods of the gate insulation film 5, areto decrease defects due to oxygen shortage in the gate insulation film 5in the case of physical forming method, and to decrease oxidation ofultrafine particles 4 a 1 present in the underlying charge retentionlayer 4 in the case of chemical forming method.

Now, an oxidation reduction treatment method according to the presentinvention which solves the above-mentioned problems, will be describedusing as an example of a construction that the charge retention layer 4comprises metal ultrafine particles and a matrix insulator made of anoxide, and that the gate insulation film 5 is an oxide formed by using aphysical forming method. Here, the tunnel insulation film 3 is assumedto be an oxide.

An oxidizing agent for removing defects due to oxygen shortage in theoxide, and a reducing agent for reducing the oxidized metal ultrafineparticles, are assumed to satisfy the following standards. First of all,the oxidizing agent has to be a material having sufficient oxidizingpower for oxidizing an easily oxidizable material such as Si, but notoxidizing a hardly oxidizable material such as Ni or W. Meanwhile, thereducing agent has to be a material satisfying a condition that it canreduce a hardly oxidizable material such as Ni or W but it does notreduce an easily oxidizable material. Here, hardly oxidizable and easilyoxidizable are terms defined by using a formation free energy forforming an oxide as described above.

As an oxide satisfying the above conditions, H₂O, NO₂, N₂O₄, NO, N₂O,SO₂, SO₃, CO₂, CO or HClO may, for example, be used for oxidizing Si.Further, as a reducing agent satisfying the above conditions, H₂, NH₃,N₂H₄, N₂H₂, CO or CH₄ may, for example, be used. Especially, using H₂Oas an oxidizing agent and using H₂ as a reducing agent is the mostexcellent for such reasons that influence of residual by-product isrelatively small, they are extremely widely used in a conventionalsemiconductor manufacturing process, there are many academic andtechnical knowledges already obtained for these gases, and that handlingof these gases is relatively easy.

Here, e.g. O₂ or O₃ may be used as an oxidizing agent, but there occursproduction problems such that these materials have extremely strongoxidizing power and they oxidize metal ultrafine particles that aresupposed to be reduced, whereby the equilibrium condition at whichreduction reaction becomes dominant moves to a high temperature side. Ina case of using these strongly oxidizing agent for oxidizing defects dueto oxygen shortage in an oxide, it is preferred to use e.g. H₂ havinghigh reactivity with the above e.g. O₂ or O₃, as a reducing agent, sothat they sufficiently react to produce e.g. H₂O gas before they areintroduced as treatment atmosphere, and use the produced reacted productas an oxidizing agent.

Next to H₂O and H₂, a nitrogen type compound is preferred as anoxidizing agent. Here, in this case, it is necessary to note generationof nitrogen compound as a by-product, and it is necessary toappropriately remove such a nitrogen compound. On the other hand, acarbon type compound or a sulfur type compound are not preferred sincesolid by-product such as graphite, a carbon compound or a sulfurcompound tends to be precipitated and removal of these by-productsbecomes necessary. From now, for convenience of explanation, it isassumed that H₂O is used as an oxidizing agent, H₂ is used as a reducingagent and each of the above oxides is SiO₂.

FIG. 2 is a view for illustrating oxidation reduction conditions in aconstruction that ultrafine particles are made of W or Ni and a matrixinsulator is made of SiO₂. In the oxidation method of the matrixinsulator and the reduction method of ultrafine particles according tothe embodiment of the present invention, a mixed gas of H₂O gas and H₂is used as an atmospheric gas. In FIG. 2, the vertical axis represents apartial pressure ratio (hereinafter referred to as H₂ partial pressureratio to H₂O) of H₂ based on H₂O, the lateral axis represents atemperature (° C.). Each of the curves shown in FIG. 2 is calculatedunder the condition that each of H₂ and H₂O is an ideal gas having afugacity coefficient of 1.

In the calculation of curves shown in FIG. 2, a saturated vapor pressureof H₂O is used as a partial pressure of H₂O in a temperature range ofless than 100° C. Further, the curve described as “Si” indicates that Siis reduced by an atmospheric gas in a region above the curve and Si isoxidized by an atmospheric gas in a region below the curve. The curvesdescribed as “W” and “Ni” respectively, indicate the same manner.

In the treatment for removing defects due to oxygen shortage, at atemperature lower than a predetermined temperature, the reaction speedis low and the treatment time becomes long. On the other hand, at atemperature higher than the predetermined temperature, agglomeration ofmetal fine particles starts to occur or the metal and the insulator forma new compound at their interfaces, such being not preferred. Further,it is also not preferred that the matrix insulator, the gate insulationfilm and the tunnel insulation film are partially crystallized by thehigh temperature treatment.

When electric charge retained in an ultrafine particle moves through aninsulator by tunnel conduction, and when the insulator is amorphous, amaterial wave of electric charge tends to be scattered since the latticearrangement of the insulator is irregular, whereby the movement ofelectric charge to adjacent ultrafine particles, the control gate andthe semiconductor substrate by the tunnel conduction, is suppressed. Onthe other hand, when the insulator is crystalline, since its lattice isregularly arranged, the material wave of electric charge is hard to bescattered, the movement by the tunnel conduction becomes relativelyeasier than the case of amorphous. This state is not preferredconsidering the characteristics required for the charge retention layer,and the gate insulation film and the tunnel insulation film. From thesereasons, the oxidation reduction treatment in the present invention ispreferably carried out in a temperature range of from about 600° C. to900° C., and more preferably in a range of from 700° C. to 800° C.

Further, in an actual oxidation reduction treatment, a sampleexperiences a temperature history that the sample in a state of roomtemperature is moved into an oxidation reduction treatment furnace,subjected to an oxidation reduction treatment at a predeterminedtemperature, and thereafter, moved to the outside of the oxidationreduction treatment where the temperature is a room temperature.However, during the oxidation reduction treatment, it is necessary tosatisfy the oxidation reduction conditions in the entire temperaturerange that the sample wafer experiences. Considering this point, controlof partial pressure ratio of the atmospheric gas is important.

For example, when the ultrafine particles are made of W, when thetreatment is carried out at a treatment temperature of 750° C., the H₂partial pressure ratio to H₂O may be within a range of from 10¹ to 10⁸from FIG. 2. However, at a temperature lower than this range, at a timeof e.g. moving the sample into or out from the oxidation reductiontreatment furnace, the partial pressure ratio of H₂ to H₂O needs to beincreased, for example, to about 10⁷ or higher at a room temperature toavoid oxidation of W. Accordingly, at a time of moving the sample intoor out from the oxidation reduction treatment furnace, it is necessaryto sufficiently decrease the H₂O gas partial pressure in the treatmentfurnace, and for this purpose, it is necessary to stop supply of H₂O gasand sufficiently discharge the gas to the outside of the furnace.

At this time, by once evacuating the inside of the oxidation reductionfurnace to a pressure of about 10⁻² Pa or lower, followed by introducingH₂ gas, it is possible to securely discharge H₂O gas, such being morepreferred. Meanwhile, when the ultrafine particles are made of Ni, thelower limit value of the H₂ partial pressure ratio to H₂O remarkablydecreases to about 10⁻², and the temperature range meeting the oxidationreduction treatment according to the present invention, is wide.Further, when a plurality of types of metals are employed in a sample,it is preferred to accommodate the treatment condition to the conditionof metal material having the narrowest conforming condition range.

By appropriately carrying out the oxidation reduction treatment, it ispossible to avoid oxidation of the metal ultrafine particles or reducethe oxidized portion, and at the same time bonding oxygen atoms withoxygen shortage type defects or free valencies of the oxide adjacent tothe metal ultrafine particles. As a result, it becomes possible toimprove charge retention performance of a nonvolatile semiconductormemory element using metal ultrafine particles as a floating gate.However, there is a case where as a side effect of the above oxidationreduction treatment method, hydrogen atoms enter into an atomic bondingnetwork of the oxide, and bond with oxygen atoms to form OH groups tocut or terminate the bonding network.

Since the OH groups may adversely affect e.g. the melting point and theinsulation performance of the oxide, it becomes necessary to remove theOH groups formed by carrying out the above oxidation reductiontreatment. For this reason, after the above oxidation reductiontreatment, it is necessary to continuously carry out annealing(hereinafter referred to as inert atmosphere annealing) in an inertatmosphere or a reduced-pressure atmosphere, to discharge hydrogen atomsbonded with oxygen atoms and forming OH groups to the outside of thefilm.

In an inert atmosphere annealing for the purpose of removing OH groups,it is necessary to provide a thermal energy sufficient for cutting OHbonds to let the hydrogen atoms free, and to quickly discharge thegenerated H₂ to the outside of the system, and it is necessary to avoidoxidation reaction of metal ultrafine particles and reduction reactionof the oxide. For this purpose, the inert atmosphere annealing for thepurpose of removing OH groups, is preferably carried out in an inert gasor in a reduced-pressure atmosphere. Here, the inert gas orreduced-pressure atmosphere, should be controlled and maintained also attimes of moving a sample into and out from the oxidation reductiontreatment furnace.

In order to provide sufficient thermal energy to cut OH bonds, it ispreferred to set the treatment temperature to be at least 600° C. On theother hand, when the temperature is too high, agglomeration of metalultrafine particles becomes to occur, or the metal and the insulatorforms a new compound at their interfaces, such being not preferred.Further, at a high temperature, the matrix insulator, the gateinsulation film and the tunnel insulation film are partiallycrystallized, such also being not preferred.

When electric charge retained in an ultrafine particle moves through theinsulator by tunnel conduction, and when the insulator is amorphous,since the lattice arrangement of the insulator is irregular, thematerial wave of the electric charge tends to be scattered, and movementof the electric charge to adjacent ultrafine particles, the control gateor the semiconductor substrate by the tunnel conduction, is suppressed.On the other hand, when the insulator is crystalline, since the latticeis regularly arranged, the material wave of the electric charge is hardto be scattered, and movement of the electric charge by tunnelconduction becomes relatively easier than the case of amorphous. Thisstate is not preferred considering the properties required for thecharge retention layer, the gate insulation film and the tunnelinsulation film. For the above reasons, the treatment temperature ispreferably from about 600° C. to 900° C., more preferably from 700° C.to 800° C.

The oxidation reduction treatment and the inert atmosphere annealing inan inert gas atmosphere or a reduced-pressure atmosphere, may be carriedout in any step on and after forming of the charge retention layer, andit can be carried out an optional number of times. However, theoxidation reduction treatment and the inert atmosphere annealing aretreatments mainly effective for the charge retention layer, the gateinsulation film and the tunnel insulation film, and accordingly, it isthe most preferably carried out after forming of the gate insulationfilm.

In a case of carrying out the oxidation reduction treatment afterdepositing another film after forming the charge retention layer 4 andthe gate insulation film 5, it is necessary that the reaction materialis diffused in the deposited film and reaches the charge retention layer4 and the gate insulation film 5. In the same manner, in order todischarge reaction product to the outside of the system, it is necessarythat the reaction product is diffused through the deposited film to moveto the surface of the sample. Since such diffusion takes a long time, itis not preferred to carry out the treatment in a state that the aboveanother film is thickly deposited.

However, in order to repair deteriorated portions of the chargeretention layer 4 and the gate insulation film 5, or in order to repaira deteriorated portions of the control gate 6, that are caused by aplasma damage at a time of gate fabrication or other reactions, it isextremely effective to carry out the treatment again after the gatefabrication. Further, when side walls 9 are formed on gate sidefacesafter the gate fabrication, and when the forming of the sidewalls iscarried out, for example, by a CVD method, the ultrafine particles maybe oxidized in the step of depositing the sidewall films. Also in thiscase, it is preferred to carry out the above oxidation reductiontreatment and the inert atmosphere annealing again after the forming ofsidewalls.

The control gate 6 may be made of any one of a polycrystal Si containingimpurities, a metal Si compound, a metal or a complex material as acombination of a plurality of materials such as a lamination of theabove materials. In order to improve writing and erasing operationspeeds, the resistance of the control gate is preferably low, and thecontrol gate preferably has a sheet resistance of at most 5 Ω/sq, morepreferably at most 1 Ω/sq. In a case of using a polycrystal Si for thecontrol gate, when the control gate is applied to a nMOSFET, a n-typeimpurity is usually contained in the polycrystal Si, and on the otherhand, when the control gate is applied to a pMOSFET, a p-type impurityis usually contained in the polycrystal Si.

A source region 7 and a drain region 8 preferably have shallow junctionregions 7 a, 8 a respectively to make slopes of impurity concentrationsin the vicinities of connection regions of the regions 7, 8 with thechannel, to thereby weaken electric field intensity in the lateraldirection (a direction in parallel with semiconductor surface) in orderto suppress generation of excessive hot carriers. In these shallowjunction regions 7 a, 8 a, the impurity concentrations are lower and thejunction depths are shallower than those in contact regions 7 b, 8 b.

In order to form the above shallow junction regions 7 a, 8 a and thecontact regions 7 b, 8 b, sidewalls 9 are formed on gate sidefaces.Here, the gate to be provided with sidewalls 9 means an entire portionconstituted by the tunnel insulation film 3, the charge retention layer4, the gate insulation film 5 and the control gate 6. This definition isapplied hereinafter. These side walls 9 also serve to decrease overlapregions of the gate with the source region 7 and the drain region 8,particularly overlap regions of the gate with the contact regions 7 a, 8b being high concentration impurity regions. By decreasing overlapregions, it is possible to decrease parasitic capacitance formed inthese regions, and to provide effects of high speed operation and lowpower consumption of the element. Further, for the purpose ofsuppressing leakage between the source and the drain in a microelement,it is preferred to form a halo ion implantation region 10.

As described above, in the process for producing nonvolatilesemiconductor memory element according to the embodiment of the presentinvention, in a nonvolatile semiconductor memory element having aconstruction that a hardly oxidizable material composed of e.g. W, Ni orCo is used as a ultrafine particle floating gate or a single floatinggate, and an oxide of an easily oxidizable material such as SiO₂ is usedas an insulator surrounding the floating gate, wherein the ultrafineparticle floating gate or the single floating gate and the insulator aresimultaneously formed by using a physical forming method, it is possibleto bond oxygen atoms with e.g. oxygen shortage type defects or freevalencies in an insulator such as SiO₂ while the ultrafine particlefloating gate or the single floating gate is not oxidized or while it isreduced, whereby it is possible to improve insulation performance of theinsulator surrounding the floating gate such as the metal ultrafineparticle floating gate, and to decrease the ratio of oxidized ultrafineparticles in the floating gate, and it is possible to produce anonvolatile semiconductor memory element having high charge retentionperformance.

Further, in a nonvolatile semiconductor memory element having aconstruction that a hardly oxidizable material composed of e.g. W, Ni orCo is used as an ultrafine particle floating gate or a single floatinggate and an oxide of an easily oxidizable material such as SiO₂ is usedas an insulator surrounding the floating gate, wherein the ultrafineparticle floating gate or the single floating gate is formed by using aphysical forming method, it is possible to bond oxygen atoms with oxygenshortage type defects or free valencies in an insulator such as SiO₂while the ultrafine particle floating gate or the single floating gateis not oxidized or while it is reduced, whereby it is possible toimprove insulation performance of the insulator surrounding the floatinggate such as the metal ultrafine particle floating gate, and to decreasethe ratio of oxidized metal ultrafine particles in the floating gate,and it is possible to produce a nonvolatile semiconductor memory elementhaving high charge retention performance.

Further, in a nonvolatile semiconductor memory element having aconstruction that a hardly oxidizable material composed of e.g. W, Ni orCo is used as an ultrafine particle floating gate or a single floatinggate, and an oxide of an easily oxidizable material such as SiO₂ is usedas an insulator surrounding the floating gate, wherein the ultrafineparticle floating gate or the single floating gate is formed by using aphysical forming method, and wherein after a first insulator formedsimultaneously with the floating gate is selectively removed, a secondinsulator is formed by using a physical forming method or a chemicalforming method; it is possible to bond oxygen atoms with oxygen shortagetype defects or free valencies in an insulator of e.g. SiO₂ while theultrafine particle floating gate or the single floating gate is notoxidized or while it is reduced, whereby it is possible to improveinsulation performance of the insulator surrounding the floating gatesuch as the metal ultrafine particle floating gate, and to decrease theratio of oxidized metal ultrafine particles in the floating gate, and tothereby produce a nonvolatile semiconductor memory element having highcharge retention performance.

Further, since an oxide of the first easily oxidizable materialcontaining relatively large amount of defects due to oxygen shortagesuch as SiO₂ in a tentative forming layer formed by a physical formingmethod, is selectively removed and since an oxide of the second easilyoxidizable material having less defects due to oxygen shortage, issubsequently deposited, it is possible to produce a nonvolatilesemiconductor memory element having further few defects due to oxygenshortage.

Further, in a range of from 0° C. to 1,200° C., the oxidizing gasappropriately oxidizes the easily oxidizable material such as Si withoutoxidizing the ultrafine particle floating gate or the single floatinggate, and the reducing gas can appropriately reduce the ultrafineparticle floating gate or the single floating gate without reducing theoxide of easily oxidizable material such as SiO₂, and accordingly, it ispossible to regulate oxidation power of the oxidizing gas to be used andreducing power of the reducing gas to be used, to suitably carry out theheat treatments of the above oxidation and reduction, and to therebyproduce a nonvolatile semiconductor memory element having high chargeretention performance.

Further, since hydrogen and water vapor, that have sufficient experienceof use in a field of semiconductor is element manufacturing and easy tobe handled, are used as mixed gases for oxidation and reduction, it ispossible to produce a nonvolatile semiconductor memory element havinghigh charge retention performance easily and safely with goodreproducibility.

Further, after the oxidation reduction treatment is carried out, a heattreatment is carried out in a predetermined inert atmosphere or underreduced-pressure, it is possible to effectively remove by-products suchas OH groups which may remain after the oxidation-reduction treatment inthe production of nonvolatile semiconductor memory element. Here, the OHgroups which may remain after the oxidation-reduction treatment, maycause adverse effect such as lowering of melting point of the oxide ordeterioration of insulation properties.

As described above, the nonvolatile semiconductor memory elementaccording to the embodiment of the present invention, has an effectproduced by the process for producing nonvolatile semiconductor memoryelement of the present invention, and has high charge retentionperformance and element performance.

EXAMPLES

Specific Examples based on the above-mentioned embodiments of thepresent invention, are described below.

Example 1

FIG. 3 is a process flow chart for explaining a process for producingnonvolatile semiconductor memory element according to Example 1. In thisExample, process steps for producing peripheral circuit portions such aselement selection transistors or signal amplification circuit, areomitted, and only process steps for producing memory elements aredescribed.

First of all, element isolations 2 are formed on a surface of asemiconductor substrate 1 made of a single crystal Si doped with p-typeimpurities (S101; refer to FIG. 4). Then, ion implantation for adjustingthreshold voltage is carried out (S102; refer to FIG. 5). Here, beforethis ion implantation, a film called as screen oxide film 21schematically shown in FIG. 5 is formed by using Si thermal oxidation.As ions to be implanted, BF₂ ⁺ ions are employed, and the semiconductorsubstrate is tilted by 7° to the incident direction of implanted ions sothat the implanted ions do not cause channeling of the semiconductorsubstrate. Here, “channeling” means a phenomenon that implanted ionsdeeply penetrate into a semiconductor substrate without collidingcrystal lattice.

Then, the above screen oxide film 21 is removed so that the surface ofthe semiconductor substrate 1 is exposed, and a tunnel insulation film 3is formed on the surface of the semiconductor substrate 1 (S103; referto FIG. 6). The forming of the tunnel insulation film 3 is carried outby forming a Si thermal oxide film by thermally oxidizing thesemiconductor substrate 1 surface in a dry O₂ atmosphere. Here, thethickness of the tunnel insulation film 3 is 3 nm.

Then, on the tunnel insulation film 3 formed in the step S103, a chargeretention layer 4 is formed (S104; refer to FIG. 7). The forming ofcharge retention layer 4 is carried out by a method of simultaneouslysputtering a metal target and an insulator target. By this method, aconstruction that metal ultrafine particles are densely dispersed in amatrix insulator, is obtained in self-organization manner. As the metaltarget, a Ni metal plate is employed, and as the insulator target, aSiO₂ plate is employed.

Here, the formation free energies of Ni and Si for forming their oxides,are, for example, at a temperature of 800° C., −286.0 kJ/mol for Ni(reaction formula: 2Ni+O₂→2NiO) and −717.5 kJ/mol for Si (reactionformula: Si+O₂→SiO₂), and the formation free energy of Si for forming anoxide of Si is lower. Sputtering is carried out under the conditionsthat the surface area ratio between a Ni target and a SiO₂ target is15:85, the atmospheric gas is Ar, the pressure is 0.5 Pa and thesupplied power is 200 W. The thickness of the charge retention layer 4is made to be 5 nm.

A cross section of the charge retention layer 4 formed under the aboveconditions, is observed by a transmission electron microscope (TEM), andit is confirmed that Ni ultrafine particles having an average diameterof 2 nm are dispersed in an amorphous SiO₂ matrix insulator. Further,using an energy dispersive fluorescent X-ray measurement (EDX), theatomic ratio between Ni elements and Si elements in the formed chargeretention layer 4 is measured, and from the value and the diameters ofthe Ni ultrafine particles, an area density of Ni ultrafine particlesare estimated, and as a result, it is 8×10¹²/cm².

However, from data of Rutherford backscattering (RBS) method, it isconfirmed that the number of oxygen atoms is less than twice of thenumber of Si atoms in the matrix insulator (SiO₂) 4 b, and that oxygenshortage type defects 4 c are present, and from data of electron spinresonance (ESR) method, a resonance absorption peak indicating thepresence of free valencies (dangling bonds) 4 d is detected.

Then, a gate insulation film 5 is formed on the charge retention layer 4formed in the step S104 (S105; refer to FIG. 8). The forming of gateinsulation film 5 is achieved by carrying out sputtering using a SiO₂target in a Ar gas atmosphere under the conditions that the pressure is0.5 Pa and the supply power is 200 W. Here, the thickness of the gateinsulation film is made to be 10 nm. Also with respect to the gateinsulation film 5 formed in step S105, evaluation is carried out byRutherford back scattering (RBS) method and electron spin resonance(ESR) method in the same manner as the above charge retention layer 4,and as a result, it is confirmed that oxygen shortage type defects 5 band free valencies 5 c are present.

Then, in order to remove the above oxygen shortage type defects 4 c, 5 band free valencies 4 d, 5 c, an oxidation reduction treatment describedbelow is carried out (S106; refer to FIG. 9). An oxidation reductiontreatment furnace is heated to 800° C., H₂ functioning as a reducingagent is supplied to the oxidation reduction treatment furnace tosufficiently substitute an atmosphere in the oxidation reductiontreatment furnace by H₂, and thereafter, H₂O gas produced by burning H₂with O₂ in an adjacent separate treatment furnace, is supplied so thatits flow rate becomes the same as that of H₂. In this case, the H₂partial pressure ratio to H₂O in the oxidation reduction treatmentfurnace is 1, and in this state, Ni is reduced and Si is oxidized asshown in FIG. 2. A sample wafer is moved into the oxidation reductiontreatment filled with the above atmosphere, and oxidation treatment iscarried out for 30 minutes.

A monitor sample obtained by carrying out the above oxidation reductiontreatment is evaluated by a Rutherford back scattering (RBS) method andan electron spin resonance (ESR) method, and as a result, the elementnumber ratio between Si and oxygen is 2 according to the RBS method, andthe resonance absorption peak intensity of electromagnetic waves is abackground level according to the ESR method, whereby it is confirmedthat oxygen shortage type defects 4 c, 5 b and free valencies 4 d, 5 cthat are present before the oxidation reduction treatment, aredisappeared. Further, an evaluation is made by using an electron beamdiffraction (ED) method, and as a result, only diffraction pattern offace-centered cubic crystal is detected, but diffraction pattern of Nioxide such as NiO is not detected, and accordingly, it is confirmed thatNi does not form an oxide by the oxidation reduction treatment but itremained in a state of Ni as it is.

However, when an absorption spectrum of infrared rays is measured byusing a Fourier transformation infrared spectrometry (FTIR) method, andas a result, a infrared absorption derived from OH groups 4 e in theSiO₂ film of the charge retention layer 4 and OH groups 5 d in the SiO₂gate insulation film 5, are confirmed. Namely, presence of OH groups inthe matrix insulator 4 b of the charge retention layer 4 and the gateinsulation film 5 are confirmed. In order to remove such OH groups,after the above oxidation reduction treatment is finished, inertatmosphere annealing of the sample wafer is subsequently carried out(S107; refer to FIG. 10).

The inert atmosphere annealing is carried out at 800° C. for 10 minutesafter the atmosphere in the oxidation reduction treatment is substitutedby N₂ gas so that the atmosphere becomes inert. The atmosphere in theoxidation reduction treatment furnace at this time is sampled, and theH₂ partial pressure ratio to H₂O is measured by a gas chromatographspectrometer, and as a result, H₂ partial pressure ratio to H₂O is about10⁸. When a FTIR measurement is carried out by using a monitor sampleobtained by the above inert atmosphere annealing in the manner describedabove, it is confirmed that the infrared absorption derived from OHgroups is disappeared.

Then, a thin film for control gate 6 is formed on the gate insulationfilm 5 (S108; refer to FIG. 11). As the thin film for control gate 6, apolycrystal Si film is deposited by using a low pressure CVD (LPCVD)method. At this time, a mixed gas of SiH₄ with PH₃ is used as afilm-forming gas, and P is doped as impurities.

After the thin film for control gate 6 is formed in step S108, gatefabrication is carried out (S109; refer to FIG. 12). The gatefabrication is carried out by forming a resist pattern by an ArFexposure apparatus, and dry etching the thin film for control gate 6,the gate insulation film 5, the charge retention layer 4 and the tunnelinsulation film 3 by using a halogen type gas. Subsequently, a wetetching is carried out to completely remove Ni ultrafine particles.

Here, in order to evaluate residual amount of Ni ultrafine particles, aNi—SiO₂ type thin film of 5 nm thick similar to the charge retentionlayer, is formed, it is subjected to a wet etching treatment similar toone described above, and residual amount of Ni on the surface of thesemiconductor substrate 1 after the wet etching treatment is analyzed bya total reflection fluorescent X-ray analysis (TXRF). As a result, theresidual amount of Ni is less than detection limit (about 10⁹ atom/cm²),and Ni is not detected.

Then, ion implantation is carried out to form shallow junction regions 7a, 8 a (S110; refer to FIG. 13). In order to make junction depthshallow, As⁺ is implanted at low energy so that the range distance ofimplanted ions becomes short. After ion implantation is carried out instep S110, a SiO₂ film is deposited by using a LPCVD method, and thefilm is subjected to anisotropic etching to form sidewalls 9 (S111;refer to FIG. 14). Then, using these sidewalls 9 as a mask, ionimplantation is carried out to form contact regions 7 b, 8 b (S112;refer to FIG. 15).

The ion implantation for forming the contact regions 7 b, 8 b is carriedout at a high implantation energy to make the injunction depth of thecontact regions 7 b, 8 b deeper than the junction depth of the shallowjunction regions 7 a, 8 a. After ion implantation is carried out in stepS112, in order to activate the implanted As, an annealing (hereinaftersimply referred to as activation annealing) for activating impurities iscarried out by using a RTA (rapid thermal annealing) apparatus in areduced-pressure atmosphere at 1,000° C. for 5 seconds (S113).

Then, as shown in FIG. 16, BF₂ ⁺ ions are implanted from an obliquedirection to a normal line to the substrate surface of the semiconductorsubstrate 1 (S114), and the implanted B (boron) are subjected to anactivation annealing (S115) at 800° C. for 10 seconds by using a RTAapparatus, to form halo ion implantation regions 10. Then, NSG(non-doped silica glass) and PSG (phosphorus-doped silica glass) aredeposited to form protection films (S116).

Then, contact holes for obtaining electric conductions to the controlgate 6 and the contact regions 7 b, 8 b, are formed (S117), Al circuitpattern for electrically connecting to the control gate 6 and thecontact regions 7 b, 8 b via the contact holes, are formed (S118), andH₂ annealing is carried out to improve electric contact between thecircuit Al pattern and the Si substrate (S119). A nonvolatilesemiconductor memory element employing metal ultrafine particles as afloating gates obtained in the manner described above, has a chargeretention performance of at least 20 years in a temperature environmentof 200° C., and has a rewritable performance of more than 106 times.

Example 2

FIG. 17 is an explanation view schematically showing an example of crosssectional structure of a nonvolatile semiconductor memory elementaccording to Example 2. First of all, in the same manner as explained inExample 1, on a surface of a semiconductor substrate 1 made of singlecrystal Si doped with p-type impurities, element isolations 2 are formed(S101; refer to FIG. 4), and ion implantation is carried out to adjustthreshold voltage (S102; refer to FIG. 5).

Then, the above-mentioned screen oxide film 21 (refer to FIG. 5) isremoved so that the surface of the semiconductor substrate 1 is exposed,and a tunnel insulation film 23 is formed on the surface of thesemiconductor substrate 1 (S103; refer to FIG. 18). The forming of thetunnel insulation film 23 is carried out by thermally oxidizing andnitriding the surface of the semiconductor substrate 1 in a N₂Oatmosphere to form a SiO_(0.5)N film. Here, the thickness of the tunnelinsulation film 23 is made to be 3 nm.

Then, on the tunnel insulation film 23 formed in step S103, a chargeretention layer 24 is formed (S104; refer to FIG. 19). The chargeretention layer 24 is formed by sputtering a Co target to deposit a Cothin film. Namely, the floating gate according to Example 2 is not alarge number of isolated ultrafine particles but a single thinfilm-shaped floating gate.

Then, on the charge retention layer 24 formed in step S104, a gateinsulation film 25 is formed (S105; refer to FIG. 20). The forming ofgate insulation film 25 is achieved by forming a SiO₂ film by using aLPCVD method and using a mixed gas of evaporated TEOS(tetraethoxysilane) and oxygen as a raw material.

Here, the thickness of the gate insulation film 25 is made to be 10 nm.

Here, the formation free energies of Co and Si for forming their oxidesare, for example, at 800° C., −316.6 kJ/mol for Co (reaction formula:2Co+O₂→2CoO) and −717.5 kJ/mol for Si (reaction formula: Si+O₂→SiO₂),and the formation free energy of Si for forming an oxide of Si is lower.Forming of the above SiO₂ film is carried out at relatively hightemperature, and thus, a Co thin film 24 a 1 of the charge retentionlayer 24 is entirely or partially oxidized, to form an oxidized portion24 f (refer to FIG. 20).

Then, in order to remove the above oxidized portion 24 f by reduction,an oxidation reduction treatment described below is carried out (S106;refer to FIG. 22). FIG. 21 is a view for explaining oxidation reductionconditions in a construction that a floating gate and an insulatorsurrounding the floating gate are made of Co and SiO₂ respectively. Itis understandable from FIG. 21 that in a case of carrying out oxidationreduction treatment for oxidizing Si and reducing Co at 800° C., it issufficient that the H₂ partial pressure to H₂O is set to be about 1.This treatment condition can be applicable in the same manner also tocases of moving a sample into and out from the oxidation reductiontreatment furnace.

The atmosphere in the oxidation reduction treatment furnace is realizedin the following manner. First of all, H₂ functioning as a reducingagent is supplied into the oxidation reduction treatment furnace tosufficiently substitute the atmosphere by H₂, and subsequently, H₂Oproduced by burning H₂ with O₂ is supplied so that H₂ partial pressureto the H₂O becomes 1. Then, in order to carry out oxidation reductiontreatment, in this state, a sample wafer is moved into the oxidationreduction treatment, and held there for 30 minutes. Subsequently, aninert atmosphere annealing is carried out in N₂ atmosphere at 800° C.for 10 minutes to remove OH groups formed in the gate insulation film 25(refer to FIG. 22).

Then, in the same manner as explained in Example 1 of the presentinvention, a thin film for control gate 6 is formed (S108), a gatefabrication is carried out (S109) and ion implantation is carried out(110) to form shallow junction regions 7 a, 8 a. Then, sidewalls 9 areformed (S111), ion implantation is carried out to form contact regions 7b, 8 b (S112), an activation annealing is carried out by using a RTAapparatus (S113), ion implantation is carried out to form halo ionimplantation regions 10 (S114) and an activation annealing is carriedout again by using a RTA apparatus (S115; refer to FIG. 23).

FIG. 23 is a view schematically showing a cross sectional structure ofan element after completion of the step for forming halo ionimplantation regions 10 (S114) and the step of activation annealing(S115) in the process for producing nonvolatile semiconductor memoryelement according to Example 2 of the present invention. When the abovehalo ion implantation regions 10 are formed, in the same manner as oneexplained in Example 1 of the present invention, NSG and PSG aredeposited as protection films (S116), contact holes are formed (S117),Al circuit pattern is formed (S118) and H₂ annealing is carried out toimprove electric contact between the Al circuit pattern and the Sisubstrate (S119). A nonvolatile semiconductor memory element employing aCo thin film as a floating gate obtained in the following process has acharge retention performance of at least 20 years in a temperatureenvironment of 200° C.

Example 3

FIG. 24 is an explanation view schematically showing an example of crosssectional structure of a nonvolatile semiconductor memory elementaccording to Example 3 of the present invention. First of all, in thesame manner as ones explained in Example 1 and Example 2 of the presentinvention, on a surface of a semiconductor substrate 1 made of singlecrystal Si doped with p-type impurities, element isolations 2 of STItype are formed (S101; refer to FIG. 4), and ion implantation foradjusting threshold voltage is carried out (S102).

After removing a screen oxide film, a tunnel insulation film 33 made ofa HfO₂ silicate (HfSi_(x)O_(y)) type high dielectric material is formedin Example 3 of the present invention. The tunnel insulation film 33 ofHfO₂ silicate type is formed by a sputtering method, and the filmthickness is made to be 3 nm. By employing such a high dielectricmaterial for the tunnel insulation film 33, short-channel effect can besuppressed and it becomes easy to selectively remove only matrixinsulator in a selective removal step of matrix insulator in a tentativeforming layer to be described later. More detail explanation of thiseffect is as follows. When a tunnel insulation film is made of the samematerial as that of matrix insulator such as SiO₂, the tunnel insulationfilm is inevitably partially removed at a time of removing the matrixinsulator. However, when the materials of the matrix insulator and thetunnel insulation film are different, for example, when they are SiO₂and a high dielectric material such as HfO₂ silicate type materialrespectively, it becomes possible to selectively remove only matrixinsulator in the tentative forming layer and to completely retain thetunnel insulation film without being removed. When the selectivity forremoving the matrix insulator is low in such as a case where the tunnelinsulation film and the matrix insulator are the same material, the filmthickness of the tunnel insulation film becomes excessively thinner thanits design value, and the variation of the film thickness increases,causing deterioration of charge retention properties of the element andincrease of variation of threshold voltage. In order to avoid suchproblems, in a nonvolatile semiconductor memory element of this examplewhose production process includes a step of removing matrix insulator ina tentative forming layer, it is extremely preferred to apply a materialdifferent from that of the matrix insulator to the tunnel insulationfilm.

Then, on the tunnel insulation film 33 formed in step S103, a chargeretention layer 34 as a tentative forming layer is formed (S104; referto FIG. 25). The forming of charge retention layer 34 is carried out inthe same manner as that explained in Example 1 under the condition thata W metal plate is employed as a metal target, a SiO₂ plate is employedas an insulator target and the ratio of surface area between thesetargets is set to 15:85. Here, the formation free energies of W and Sifor forming their oxides are, for example at 750° C., −403.4 kJ/mol forW (reaction formula: W+O₂→WO₂) and −726.2 kJ/mol for Si (reactionformula: Si+O₂→SiO₂), and the formation free energy of Si for formingthe oxide of Si is lower.

A cross section of the charge retention layer 34 formed under the aboveconditions is observed by using a transmission electron microscope(TEM), and as a result, it is confirmed that W ultrafine particleshaving an average diameter of 2 nm are dispersed in a SiO₂ matrixinsulator. Further, using an energy dispersive fluorescent X-raymeasurement (EDX), the atomic ratio between W elements and Si elementsin the formed charge retention layer 34 is measured, and from the valueand the diameters of the W ultrafine particles, an area density of Wultrafine particles are estimated, and as a result, it is 8×10¹²/cm².

However, according to the data of Rutherford backscattering (RBS)method, it is confirmed that the number of oxygen atoms is less thantwice as the Si atoms in the SiO₂ matrix insulator 34 b, and that oxygenshortage type defects 34 c are present, and from the data of electronspin resonance (ESR) method, a resonance absorption peak indicating thepresence of free valencies (dangling bonds) 34 d is detected.

Then, the SiO₂ matrix insulator 34 b of the charge retention layer 34 asthe tentative forming layer formed on the tunnel insulation film 33 isselectively removed and W ultrafine particles 34 a 1 are retained. Theselective removal of the SiO₂ matrix insulator 34 b is carried out bydry etching using a CF₄+H₂ type gas as an etching gas (refer to FIG.26).

Then, on the charge retention layer 34 formed in step S104, a gateinsulation film 35 is formed (S105; refer to FIG. 27). Forming of thegate insulation film 35 is carried out by forming a SiO₂ film by a LPCVDmethod using a mixed gas of evaporated TEOS and oxygen as a rawmaterial. Here, the thickness of the gate insulation film 35 is made tobe 10 nm. Since the forming of SiO₂ film is carried out at relativelyhigh temperature, W ultrafine particles 34 a 1 is entirely or partiallyoxidized to form an oxidized portion.

Then, in order to reduce the above oxidized portion, an oxidationreduction treatment to be described later is carried out (S106). FIG. 28is a view for illustrating oxidation reduction conditions in aconstruction that ultrafine particles are made of W, the tunnelinsulation film is made of a high dielectric material of HfO₂ silicatetype, and the gate insulation film is made of SiO₂. It is understandablefrom FIG. 28 that in a case of carrying out the oxidation reductiontreatment for oxidizing Si and Hf and reducing W in an oxidationreduction treatment furnace at a temperature of 750° C., it issufficient that the H₂ partial pressure ratio to H₂O is set to be in awide range of from about 10¹ to 10⁸.

However, at times of moving a sample wafer into and out from theoxidation reduction treatment furnace, since the temperature of thesample wafer drops to a room temperature, it is necessary to make the H₂partial pressure to H₂O to about 10⁷ or more (H₂O concentration is about0.1 ppm or lower). In order to appropriately carry out oxidationreduction in a range of from room temperature to the temperature ofoxidation reduction, the H₂ partial pressure ratio to H₂O and thetemperature are controlled so that they change along the path shown inFIG. 28.

First of all, inside of the oxidization reduction treatment furnace isevacuated to a pressure of about 10⁻³ Pa or lower, and thereafter, H₂ issupplied into the oxidation reduction treatment furnace to make thepressure to 1 atm. By this treatment, the H₂ partial pressure ratio toH₂O in the oxidation reduction treatment furnace becomes about 10⁸ ormore, in other words, H₂O becomes about 10 ppb or lower. In this state,the sample wafer is moved into the oxidation reduction treatment furnaceand the temperature is raised to 600° C. while the atmosphere ismaintained.

Then, until the temperature rises to 750° C. being an oxidationreduction treatment temperature, H₂O gas produced by burning H₂ with O₂in an adjacent separate treatment furnace is supplied into the oxidationreduction treatment furnace so that its flow rate gradually increases,and so that the H₂ partial pressure to H₂O becomes about 10² when thetemperature reaches 750° C. In this state, oxidation reduction treatmentis carried out for 30 minutes. Subsequently, the atmosphere in theoxidation reduction treatment furnace is substituted by N₂ atmosphere,and an inert atmosphere annealing for removing OH groups is carried outfor 10 minutes. The atmosphere in the oxidation reduction treatmentfurnace at this time is sampled, and its H₂ partial pressure ratio toH₂O is measured by using a gas chromatography analyzer, and as a result,the H₂ partial pressure H₂O is about 10⁸. Then, maintaining theatmosphere in this state, the sample wafer is moved to a region of lowtemperature in the oxidation reduction treatment furnace and cooled to aroom temperature.

Then, in the same manner as one explained in Example 1 of the presentinvention, a thin film for control gate 6 is formed (S108), a gatefabrication is carried out (S109), and ion implantation is carried outto form shallow junction regions 7 a, 8 a (S110). Here, the gate lengthis made to 65 nm by using an electron beam exposure apparatus. Then,sidewalls 9 are formed (S111), ion implantation is carried out to formcontact regions 7 b, 8 b (S112), an activation annealing is carried outby using a RTA apparatus (S113), ion implantation is carried out to formhalo ion implantation regions 10 (S114), and an activation annealing iscarried out again by using a RTA apparatus (S115). FIG. 29 shows aschematic cross sectional view of an element after the activationannealing (S115) is completed.

Then, in the same manner as one explained in Example 1, NSG and PSG aredeposited as protection films (S116), contact holes are formed (117), Alcircuit pattern is formed (S118), and H₂ annealing is carried out toimprove electric contact between the Al pattern and the Si substrate(S119).

Detail of the process from the above deposition of control gate 6 to theabove H₂ annealing, are the same as those explained in Examples 1 and 2except for the gate fabrication step. A nonvolatile semiconductor memoryelement employing W ultrafine particles as floating gates having a gatelength of 65 nm obtained by the above process, has a charge retentionperformance of at least 20 years in a temperature environment of 200°C., and has a to e.g. production process of nonvolatile semiconductormemory elements of other memory methods, such as ferroelectric memories(FeRAMs) or MRAMs.

The entire disclosure of Japanese Patent Application No. 2005-263792filed on Sep. 12, 2005 including specification, claims, drawings andsummary is incorporated herein by reference in its entirety.

1. A process for producing a nonvolatile semiconductor memory elementhaving a mixed or laminated structure of a hardly oxidizable materialcomposed of a hardly oxidizable element having a Gibbs' formation freeenergy for forming oxide higher than the Gibbs' formation free energy ofSi for forming oxide under the same temperature condition at 1 atm andin a temperature range of from 0° C. to 1,200° C. and an oxide of aneasily oxidizable material composed of an element having a Gibbs'formation free energy for forming oxide lower than the Gibbs' formationfree energy of Si for forming oxide under the same temperature conditionat 1 atm in the temperature range of from 0° C. to 1,200° C., and Si,the process comprising: forming a portion made of the hardly oxidizablematerial and a portion made of the oxide of the easily oxidizablematerial by a physical forming method; and carrying out a heat treatmentin a mixed gas of an oxidizing gas functioning as an oxidizing agent anda reducing gas functioning as a reducing agent, wherein the mixtureratio of the oxidizing gas and the reducing gas and the temperature arecontrolled so that the hardly oxidizable material is reduced and theoxide of the easily oxidizable material is oxidized in a temperaturerange of from 0° C. to 1,200° C.
 2. The process for producing anonvolatile semiconductor memory element according to claim 1, whereinchange amount of Gibbs' free energy of the oxidizing gas required foroxidation reaction with the easily oxidizable material is negative inthe temperature range of from 0° C. to 1,200° C., change amount ofGibbs' free energy of the reducing gas required for reduction reactionwith the oxide of the hardly oxidizable material is negative in thetemperature range of from 0° C. to 1,200° C., and change amount ofGibbs' free energy of the reducing gas required for reduction reactionwith the oxide of the easily oxidizable material is positive in thetemperature range.
 3. The process for producing a nonvolatilesemiconductor memory element according to claim 1, wherein the oxidizinggas contains H₂O and the reducing gas contains H₂.
 4. The process forproducing a nonvolatile semiconductor memory element according to claim1, wherein the heat treatment is carried out in a mixed gas of theoxidizing gas and the reducing gas so that the hardly oxidizablematerial is reduced and the oxide of the easily oxidizable material isoxidized, and subsequently, a further heat treatment is carried out in apredetermined inert gas atmosphere or under a reduced pressure.
 5. Theprocess for producing a nonvolatile semiconductor memory elementaccording to claim 4, wherein the heat treatment in an inert gasatmosphere or under a reduced pressure, is carried out at from 600° C.to 900° C.
 6. A nonvolatile semiconductor memory element, which is anonvolatile semiconductor memory element having the hardly oxidizablematerial, and produced by using the process for producing nonvolatilesemiconductor memory element as defined in claim 1.